1. Technical Field
Various embodiments of the present disclosure generally relate to a semiconductor integrated circuit, and more particularly, to a power-on reset signal generation circuit of a semiconductor memory apparatus.
2. Related Art
A semiconductor memory apparatus is driven by an applied external voltage. When the semiconductor memory apparatus is driven by the external voltage, the semiconductor memory apparatus is configured to not operate until a level of the external voltage is identical to or greater than a target voltage level. This prevents the semiconductor memory apparatus from functioning improperly at an external voltage level less than the target voltage level.
In general, a semiconductor memory apparatus has a circuit (a power-on reset signal generation circuit) for driving the internal circuits of the semiconductor memory apparatus when the external voltage level becomes identical to or greater than the target voltage level.
Referring to FIG. 1, a typical power-on reset signal generation circuit of a semiconductor memory apparatus comprises an external voltage level detector 10, a band gap voltage generation unit 20, a voltage dividing unit 30, and a power-on reset signal generation unit 40.
The external voltage level detector 10 detects the level of an external voltage VDD and generates a detection signal det. For example, the external voltage level detector 10 enables the detection signal det when the external voltage VDD has a level identical to or greater than a target voltage level.
The band gap voltage generation unit 20 generates a band gap voltage V_bg when the detection signal det is enabled. The band gap voltage generation circuit 20 may be, for example, a typical band gap circuit. The band gap voltage generation unit 20 is designed in such a manner that the target voltage level of the band gap voltage V_bg is less than the target voltage level of a division voltage V_dv.
The voltage dividing unit 30 divides the external voltage VDD and generates the division voltage V_dv.
The power-on reset signal generation unit 40 compares the division voltage V_dv with the band gap voltage V_bg and generates a power-on reset signal POR_signal.
Exemplary operations of the power-on reset signal generation circuit of the conventional semiconductor memory apparatus as discussed above, are described with reference to FIG. 2.
As the external voltage VDD is applied to the semiconductor memory apparatus, the level of the external voltage VDD rises to a preset voltage level. During the rising interval of the level of the external voltage VDD, when the level of the external voltage VDD is identical to or greater than the target voltage level, the detection signal det is enabled.
If the detection signal det is enabled, the band gap voltage V_bg is generated. The band gap voltage V_bg also rises to a predetermined voltage level.
Referring to FIG. 2, in a typical case a), when the level of the division voltage V_dv is higher than the level of the band gap voltage V_bg, the power-on reset signal POR_signal is disabled to a low level. Also, when the level of the division voltage V_dv is lower than the level of the band gap voltage V_bg, the power-on reset signal POR_signal is enabled to a high level.
In the typical case a), when the level of the external voltage VDD is identical to or greater than the target voltage level, the power-on reset signal POR_signal is enabled to a high level, is maintained at the enabled state, and is disabled to a low level.
In a non-typical case b), as the timing at which the band gap voltage V_bg is generated becomes slower than the typical case a), there is no such case that the level of the band gap voltage V_bg is higher than the level of the division voltage V_dv. Thus, the power-on reset signal POR_signal comprises a glitch component as shown in the drawing.
If the power-on reset signal POR_signal is generated as the glitch component, the power-on reset signal POR_signal is likely to disappear before it is transferred to internal circuits.
As a result, in the non-typical case b), because the power-on reset signal POR_signal is not transferred to the internal circuits, the internal circuits cannot be driven. That is to say, this causes an initial driving error of the semiconductor memory apparatus.